Go to the documentation of this file. 11 #include "epicsTypes.h" 36 #define U32_Status 0x0000 // Status Register (full) 37 #define U8_DBusRxValue 0x0000 // Distributed Data Bus Received Values 38 #define U8_DBusTxValue 0x0001 // Distributed Data Bus Transmitted Values 43 #define U32_Control 0x0004 // Control Register 48 #define U32_IrqFlag 0x0008 // Interrupt Flag Register 49 #define U32_IrqEnable 0x000C // Interrupt Enable Register 51 #define EVG_IRQ_ENABLE 0x80000000 // Master Interrupt Enable Bit 52 #define EVG_IRQ_PCIIE 0x40000000 53 #define EVG_IRQ_STOP_RAM_BASE 0x00001000 // Sequence RAM Stop Interrupt Bit 54 #define EVG_IRQ_STOP_RAM(N) (EVG_IRQ_STOP_RAM_BASE<<N) 55 #define EVG_IRQ_START_RAM_BASE 0x00000100 // Sequence RAM Start Interrupt Bit 56 #define EVG_IRQ_START_RAM(N) (EVG_IRQ_START_RAM_BASE<<N) 57 #define EVG_IRQ_EXT_INP 0x00000040 // External Input Interrupt Bit 58 #define EVG_IRQ_DBUFF 0x00000020 // Data Buffer Interrupt Bit 59 #define EVG_IRQ_FIFO 0x00000002 // Event FIFO Full Interrupt Bit 60 #define EVG_IRQ_RXVIO 0x00000001 // Receiver Violation Bit 63 #define U32_PCI_MIE 0x001C 64 #define EVG_MIE_ENABLE 0x40000000 69 #define U32_AcTrigControl 0x0010 71 #define AcTrigControl_Sync 0x00010000 72 #define AcTrigControl_Bypass 0x00020000 73 #define AcTrigControl_Divider_MASK 0x0000ff00 74 #define AcTrigControl_Divider_SHIFT 8 75 #define AcTrigControl_Phase_MASK 0x000000ff 76 #define AcTrigControl_Phase_SHIFT 0 78 #define U32_AcTrigMap 0x0014 80 #define AcTrigMap_EvtMASK 0xff000000 81 #define AcTrigMap_EvtSHIFT 24 86 #define U32_SwEvent 0x0018 88 #define SwEvent_Ena 0x00000100 89 #define SwEvent_Pend 0x00000200 90 #define SwEvent_Code_MASK 0x000000ff 91 #define SwEvent_Code_SHIFT 0 96 #define U32_DataBufferControl 0x0020 // Data Buffer Control Register 97 #define U32_DBusSrc 0x0024 // Distributed Data Bus Mapping Register 102 #define U32_FPGAVersion 0x002C // FPGA Firmware Version 104 #define FPGAVersion_TYPE_MASK 0xF0000000 105 #define FPGAVersion_FORM_MASK 0x0F000000 106 #define FPGAVersion_FORM_SHIFT 24 107 #define FPGAVersion_TYPE_SHIFT 28 108 #define FPGAVersion_VER_MASK 0x000000FF 113 #define U32_uSecDiv 0x004C // Event Clock Freq Rounded to Nearest 1 MHz 115 #define U32_ClockControl 0x0050 117 #define ClockControl_plllock 0x80000000 118 #define ClockControl_Sel_MASK 0x07000000 119 #define ClockControl_Sel_SHIFT 24 120 #define ClockControl_Div_MASK 0x003f0000 121 #define ClockControl_Div_SHIFT 16 122 #define ClockControl_EXTRF 0x01000000 // External/Internal reference clock select 123 #define ClockControl_cglock 0x00000200 126 #define U8_ClockSource 0x0050 // Event Clock Source(Internal or RF Input) 127 #define U8_RfDiv 0x0051 // RF Input Divider 128 #define U16_ClockStatus 0x0052 // Event Clock Status 133 #define U32_EvAnControl 0x0060 // Event Analyser Control/Status Register 134 #define U16_EvAnEvent 0x0066 // Event Code & Data Buffer Byte 135 #define U32_EvAnTimeHigh 0x0068 // High-Order 32 Bits of Time Stamp Counter 136 #define U32_EvAnTimeLow 0x006C // Low-Order 32 Bits of Time Stamp Counter 141 #define U32_SeqControl_base 0x0070 // Sequencer Control Register Array Base 142 #define U32_SeqControl(n) (U32_SeqControl_base + (4*n)) 144 #define SeqControl_TrigSrc_MASK 0x000000ff 145 #define SeqControl_TrigSrc_SHIFT 0 150 #define U32_FracSynthWord 0x0080 // RF Reference Clock Pattern (Micrel SY87739L) 155 #define U32_RxInitPS 0x0088 // Initial Value For RF Recovery DCM Phase 158 #define U32_SPIDData 0x0A0 159 #define U32_SPIDCtrl 0x0A4 164 #define U32_TrigEventCtrl_base 0x0100 // Trigger Event Control Register Array Base 165 #define U32_TrigEventCtrl(n) (U32_TrigEventCtrl_base + (4*(n))) 167 #define TrigEventCtrl_Ena 0x00000100 168 #define TrigEventCtrl_Code_MASK 0x000000ff 169 #define TrigEventCtrl_Code_SHIFT 0 171 #define U8_TrigEventCode(n) (U32_TrigEventCtrl(n) + 3) 173 #define EVG_TRIG_EVT_ENA 0x00000100 178 #define U32_MuxControl_base 0x0180 // Mux Counter Control Register Base Offset 179 #define U32_MuxPrescaler_base 0x0184 // Mux Counter Prescaler Register Base Offset 181 #define U32_MuxControl(n) (U32_MuxControl_base + (8*(n))) 183 #define MuxControl_Pol 0x40000000 184 #define MuxControl_Sts 0x80000000 185 #define MuxControl_TrigMap_MASK 0x000000ff 186 #define MuxControl_TrigMap_SHIFT 0 188 #define U32_MuxPrescaler(n) (U32_MuxPrescaler_base + (8*(n))) 193 #define U16_FrontOutMap_base 0x0400 // Front Output Port Mapping Register Offset 194 #define U16_FrontOutMap(n) (U16_FrontOutMap_base + (2*(n))) 199 #define U16_UnivOutMap_base 0x0440 // Front Univ Output Mapping Register 200 #define U16_UnivOutMap(n) (U16_UnivOutMap_base + (2*(n))) 205 #define U32_FrontInMap_base 0x0500 // Front Input Port Mapping Register 206 #define U32_FrontInMap(n) (U32_FrontInMap_base + (4*(n))) 211 #define U32_UnivInMap_base 0x0540 // Front Univ Input Port Mapping Register 212 #define U32_UnivInMap(n) (U32_UnivInMap_base + (4*(n))) 218 #define U32_RearInMap_base 0x0600 // Rear Univ Input Port Mapping Register 219 #define U32_RearInMap(n) (U32_RearInMap_base + (4*(n))) 224 #define U8_DataBuffer_base 0x0800 // Data Buffer Array Base Offset 225 #define U8_DataBuffer(n) (U8_DataBuffer_base + n) 230 #define U32_SeqRamTS_base 0x8000 // Sequence Ram Timestamp Array Base Offset 231 #define U32_SeqRamTS(n,m) (U32_SeqRamTS_base + (0x4000*(n)) + (8*(m))) 233 #define U32_SeqRamEvent_base 0x8004 // Sequence Ram Event Code Array Base Offset 234 #define U32_SeqRamEvent(n,m) (U32_SeqRamEvent_base + (0x4000*(n)) + (8*(m))) 237 #define SeqRam_Length (0x4000/8) 242 #define EVG_REGMAP_SIZE 0x10000 // Register map size is 64K 249 #define EVG_SEQ_RAM_RUNNING 0x02000000 // Sequence RAM is Running (read only) 250 #define EVG_SEQ_RAM_ENABLED 0x01000000 // Sequence RAM is Enabled (read only) 252 #define EVG_SEQ_RAM_SW_TRIG 0x00200000 // Sequence RAM Software Trigger Bit 253 #define EVG_SEQ_RAM_RESET 0x00040000 // Sequence RAM Reset 254 #define EVG_SEQ_RAM_DISABLE 0x00020000 // Sequence RAM Disable 255 #define EVG_SEQ_RAM_ARM 0x00010000 // Sequence RAM Enable/Arm 257 #define EVG_SEQ_RAM_REPEAT_MASK 0x00180000 // Sequence RAM Repeat Mode Mask 258 #define EVG_SEQ_RAM_NORMAL 0x00000000 // Normal Mode: Repeat every trigger 259 #define EVG_SEQ_RAM_SINGLE 0x00100000 // Single-Shot Mode: Disable on completion 260 #define EVG_SEQ_RAM_RECYCLE 0x00080000 // Continuous Mode: Repeat on completion 266 #define EVG_MASTER_ENA 0x80000000 267 #define EVG_DIS_EVT_REC 0x40000000 268 #define EVG_REV_PWD_DOWN 0x20000000 269 #define EVG_MXC_RESET 0x01000000 270 #define EVG_BCGEN 0x00800000 271 #define EVG_DCMST 0x00400000 277 #define EVG_EXT_INP_IRQ_ENA 0x01000000 279 #ifndef EVG_CONSTANTS 280 #define EVG_CONSTANTS 283 #define evgNumEvtTrig 8 284 #define evgNumDbusBit 8 285 #define evgNumFrontOut 6 286 #define evgNumUnivOut 4 287 #define evgNumSeqRam 2 288 #define evgAllowedTsGitter 0.5f 289 #define evgEndOfSeqBuf 5